As a leading technology innovator, we push the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Engineers collaborate with cross-functional groups to determine product execution path.

Additional Job Description

Digital ASIC Team is actively seeking candidates for several physical design engineering positions in our SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using state-of-the-art tools and technologies.

You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power designs such as GPU, Camera and other MM, DDR, Modem, Audio . Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction, performance, and power goals. Additional responsibilities in this role involves good understanding of functional and test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, cell placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for MMMC designs, implementing timing fixes and functional ECOs, debugging and fixing physical violations, and formal verification. The individual also should have deep knowledge on scripting and software languages including Python, PERL/TCL, Linux/Unix shell and C. This individual will design, verify, and deliver complex Physical Design solutions from netlist and timing constraints to the final product.

Qualifications

- Bachelor's /Masters degree in Science, Engineering, or related field

Preferred Qualifications

2+ years industry experience/coursework in the following areas:

- Physical Design

- Place & Route tool experience on Cadence Innovus and/or Synopsys Fusion Compiler

- Timing closure experience in Synopsys PTSI

- Formal verification experience

- Power domain analysis experience

- Physical verification experience