Job Details:

Job Description:

As part of IPG (Intellectual Property Group), you will be developing state of the art mixed signal analog intellectual property.

You will be part of an experienced team specialized in transistor-level simulation for analog and mixed-signal designs, you will also have exposure to different Computer-Aided Design tools used in Intel silicon design across multiple technology nodes. Closely working with a highly skillful team, you will participate in a broad set of activities, including (but not limited to):

schematics capture,
pre layout simulation,
layout planning,
post layout simulation,
mixed signal verification,
use of different sign off flows to assure quality of the design and its integration to SOC (System On Chip) level.

Qualifications:

Minimum Qualifications,

You must possess the below minimum qualifications to be initially considered for this position:

Enrolled in a MS/Ph.D. program in Electrical Engineering (at least 1 year remaining as an active student).
6+ months of experience in one or more of the following: Building blocks for High-Speed Serial Links (Tx, Rx, DLL, PLL, PI, LDO, AD/DA converters, etc.).
Intermediate to advanced English level.
Must have unrestricted - permanent right to work in Mexico.

Preferred Qualifications,

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates:

Experience in simulation and characterization of analog circuits.
Knowledge of commercial circuit simulators (Cadence Design Environment).
Experience with Linux operating system.
Experience with scripting (TCL, Phyton, Perl) and/or Cadence Skill Language is a plus.

Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research and relevant previous job and/or internship experience.

A candidate who accepts an offer of employment in Mexico is required to present their own personal identification information and numbers for the following: Mexican Security Number (NSS), Tax Identification Number (RFC) and CURP identification number.

Job Type:
Student / Intern

Shift:
Shift 1 (Mexico)

Primary Location:
Mexico, Guadalajara

Additional Locations:

Business group:
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A

Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.