The candidate

• Understands different PTE test requirements and vector deliverables from DFT, DV
• Create VTRAN setup for ATPG, MBIST & Functional vectors for ATE and GG platforms
• Uses vtran tool to translate ATPG, MBIST, Functional vectors from stil or fsdb to ATE and GG friendly binary files
• Understands TSS & generate reports and metrics for vector delivery, FTRV, Phasing
• Collaborate with DFT team to bring up VT simulation environment, run FTRV checks pre-silicon
• Collaborate with DFT-DV teams to identify power sensitive tests and create FSDB for ptpx analysis and help PTE plan mitigation works
• Collaborate DTECH team to overlay thermal issues from silicon to PTPX and identify gaps in methodology
• Has experience in 93K tester, Revision control (GIT preferred)
• Has expertise with scripting with Python and code development using Java/C++ for Test method development
• C++, Java, Python programming required.
• Electrical Engineering Bs, Ms or PhD.